1. Technical Field
The present invention relates to a method and apparatus for controlling supply voltage of clock and data recovery circuit.
2. Background Art
Clock and data recovery circuit is an apparatus which recovers a clock signal which is synchronized to a received digital input signal, and further recovers digital data by using the recovered clock signal. The clock and data recovery circuit has been widely used in LANs for high-speed data transmissions, wireline and wireless communications and optical communications, disc drives, display data transmissions and data transmissions between chips, etc.
Conventional clock and data recovery circuits use a fixed supply voltage regardless of data transmission speeds of received digital input signals. Thus, power consumption for the clock and data recovery circuit is similar regardless of high or low data transmission speeds of received digital input signals. This is inefficient in terms of energy consumption since it means that energy consumption used for recovering received data per a bit is higher when data transmission speed of a received digital input signal is low.